Part $2-$ Pipelining and Hazards $(60$pts$)$ Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a five$-$stage pipelined datapath: add $s$3,$ $s$1,$ $s$0$ lw $s$2,4($$s$3)$ lw $s$1,0($$s$4)$ or $s$2,$ $s$3,$ $s$2$ sw $s$2,0($$s$3)$ The initial state of the data memory is The initial state of the register table is a$)$ If there is no forwarding or hazard detection, what is the final value of registers $s$0$~$s$4?$ After the fifth instruction will there be an exception and why? b$)$ If there is no forwarding or hazard detection, insert NOPs to ensure correct execution of the code $3$ c$)$ Now, change and$/$or rearrange the code to minimize the number of NOPs needed. You can assume register $t$0$ can be used to hold temporary values in your modified code. d$)$ If the processor has forwarding and a hazard detection unit, what is the final value of registers? e$)$ In the multi$-$cycle pipeline diagram, mark up the pipeline to show the forwarding and stalls needed to execute the following instructions on the pipelined MIPS processor. f$)$ In the multi$-$cycle pipeline diagram, mark the resources used for each of the $5$ instructions. Part $2-$ Pipelining and Hazards $(60$pts$)$

Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a five$-$stage pipelined datapath:

$```$

add $s$3,$ $s$1,$ $s$0$

lw $s$2,4($$s$3)$

$1$w $s$1,0($$s$4)$

or $s$2,$ $s$3,$ $s$2$

sw $s$2,0($$s$3)$

$```$

The initial state of the data memory is

The initial state of the register table is

a$)$ If there is no forwarding or hazard detection, what is the final value of registers $\backslash$$s$0\backslash$$s$4?$ After the fifth instruction will there be an exception and why?

b$)$ If there is no forwarding or hazard detection, insert NOPs to ensure correct execution of the code c$)$ Now, change and$/$or rearrange the code to minimize the number of NOPs needed. You can assume register $\backslash$$t$0$ can be used to hold temporary values in your modified code.

d$)$ If the processor has forwarding and a hazard detection unit, what is the final value of registers?

e$)$ In the multi$-$cycle pipeline diagram, mark up the pipeline to show the forwarding and stalls needed to execute the following instructions on the pipelined MIPS processor.

f$)$ In the multi$-$cycle pipeline diagram, mark the resources used for each of the $5$ instructions.

$4$