Part A $[2\mathrm{.}5$ marks$]$ Show how you can wire a JK flip$-$flop to implement a T flip$-$flop behaviour.

Part $B[2\mathrm{.}5$ marks$]$ Show how you can wire a JK flip$-$flop to implement a D flip$-$flop behaviour.

Part C $[2\mathrm{.}5$ marks$]$ What is the required input for the flip$-$flops in the following table?

$\backslash$table$[[$Q$($t$),$Q$($t$+1),$D$,$J$,$K$,$T$],[0,0,,,,],[0,1,,,,],[1,0,,,,],[1,1,,,,]]$

Part $D[2\mathrm{.}5$ marks$]$ What is the symbol for a D flip$-$flop that changes state on the clock's falling edge?

$[$Also$,$ did you remember to add the clock wires in Parts A and B above?$]$