Part A: Logic GatesImplementation

Download the $$Assignment $1$ zip file, unzip it$,$ you will see two sub$-$folders as following:

$$ HardwareSimulator, which contains the tools $($software$)$ we are going to use.

$$ SkeletonCodes: it contains $15$ chips, for each chip there are three type of files: $.$hdl$,.$cmp$,$ and

$.$tst$.$

ID Chip $($HDL$)$ Description Test Script Compare File

$1$ Not Not gate Not.tst Not.cmp

$2$ And And gate And.tst And.cmp

$3$ Or Or gate Or$.$tst Or$.$cmp

$4$ Xor Xor gate Xor.tst Xor.cmp

$5$ Mux Mux gate Mux.tst Mux.cmp

$6$ DMux DMux gate DMux.tst DMux.cmp

$7$ Not$1616-$bit Not Not$16.$tst Not$16.$cmp

$8$ And$1616-$bit And And$16.$tst And$16.$cmp

$9$ Or$1616-$bit Or Or$16.$tst Or$16.$cmp

$10$ Mux$1616-$bit multiplexor Mux$16.$tst Mux$16.$cmp

$11$ Or$8$Way Or$($in$0,$in$1,...,$in$7)$ Or$8$Way.tst Or$8$Way.cmp

$12$ Mux$4$Way$1616-$bit$/4-$way mux Mux$4$Way$16.$tst Mux$4$Way$16.$cmp

$13$ Mux$8$Way$1616-$bit$/8-$way mux Mux$8$Way$16.$tst Mux$8$Way$16.$cmp

$14$ DMux$4$Way $4-$way demultiplexor DMux$4$Way.tst DMux$4$Way.cmp

$15$ DMux$8$Way $8-$way demultiplexor DMux$8$Way.tst DMux$8$Way.cmp

Each group needs to finish the implementation for all $15$ chips. The workload is divided into several sets.

Use the $$Assignment Set Sheet$($distributed in class, Sept. $7),$ discuss with your group members and

decide which set you should do$.$

The ID for each chip indicates its complexity. Larger ID may be more complex. You may begin by

implementing the simpler chips, and use the chips you built to implement more complex ones. You can

cooperate with your group members and use their simpler chips to build your more complicated chips,

or you may build the simpler ones by your own.

The chips you build in this assignment will be used as basic components in further implementation.

Solving procedure for each chip:

$1.$ Truth table for ID $4,5,6$

$2.$ Disjunctive normal form expression for ID $4,5,6$