Pick a 3 bit maximal length LFSR as your CRC. Draw the CRC FSM. Number of states? Label inputs and outputs. The inputs are single bits from the incoming data stream and are exor'd with the feedback bit. The outputs are the state. Is it deterministic? Is it time or event triggered? Assume an input of 0000000000 (First bit to enter CRC is on the RHS), what is the signature (final state)? The initial state of the CRC IS 000. (assume this was the error free packet) Assume instead an input of 0100000000 (First bit to arrive on the RHS), what is the signature? The second last bit to arrive is in error. The initial state of the CRC is 000. Did the signature (last state) indicate an error? That is, was the fault free and faulty signature (final states different)? What does ethernet do on a CRC error? What does wifi do? Pick a 3 bit maximal length LFSR as your CRC. Draw the CRC FSM. Number of states? Label inputs and outputs. The inputs are single bits from the incoming data stream and are exor'd with the feedback bit. The outputs are the state. Is it deterministic? Is it time or event triggered? Assume an input of 0000000000 (First bit to enter CRC is on the RHS), what is the signature (final state)? The initial state of the CRC IS 000. (assume this was the error free packet) Assume instead an input of 0100000000 (First bit to arrive on the RHS), what is the signature? The second last bit to arrive is in error. The initial state of the CRC is 000. Did the signature (last state) indicate an error? That is, was the fault free and faulty signature (final states different)? What does ethernet do on a CRC error? What does wifi do