Pipelined processor $[25$ points$]$

Please consider the following $7$ stage pipelined processor $($depicted below$).$ The pipeline is

similar to the standard $5$ stage pipeline with the exception that the icache $($IF stage$)$ and dcache

$($MEM stage$)$ are both pipelined with a latency of $2$ cycles. Results from cache reads are

available at the end of $2$ cycles. As usual, the branch compare is calculated and the new PC

loaded during the ID stage.

Consider the following codes.

Loop: lw $$2,0($$$4)$

add $$1,$$$1,$$$2$

add $$5,$$$5,$$$1$

addi $$4,$$$4,4$

addi $$3,$$$3,-1$

bgez $$3,$ Loop

$($a$)[5$ points$]$ Identify all read$-$after$-$write dependencies in the code above. You should draw

circles around two registers that exhibit the dependency and connect them with an arrow.

$($b$)[10$ points$]$ Assume the pipelined processor provides full forwarding and a hazard

detection logic. Please fill the multi$-$cycle pipelined diagram. Stall cycles can be expressed

by inserting the dash $(--).$ Note that MEM$1/2$ are same as M$1/$M$2.$

$($c$)[7$ points$]$ To reduce the stall cycle, the compiler can reschedule the code. Please write

down the best optimized code sequence.