please answer all my questions right with steps quickly please A synchronous circuit comprises of four distinct key elements, please select the most appropriate from the following.

Question $1$ options:

A$)$ Input$/$Output signals, B$)$ Flip$-$Flops, C$)$ Combinational Logic based circuitry, D$)$ Clock signal.

A$)$ Input$/$Output signals, B$)$ Combinational Logic based circuitry, C$)$ Memory, D$)$ Reset signal.

A$)$ Input$/$Output signals, B$)$ Flip$-$Flops, C$)$ Memory, D$)$ Clock signal.

A$)$ Flip$-$Flops, B$)$ Combinational Logic based circuitry, C$)$ Reset signal, D$)$ Clock signal.For the given simplified circuit structure containing $5$ key functional blocks $($A$-$E$),$ with individual

propagation delays $($shown within each block$)$ determine the Latency and approximate maximum

data input frequency for the circuit $($Unpiplined$)$ and if the circuit was appropriately Pipelined.

Unpipelined:

Latency $=9\mathrm{.}3ns,$ Maximum data input frequency $=107MHz$

Pipelined:

Latency $=13\mathrm{.}2ns,$ Maximum data input frequency $=303MHz$

Unpipelined:

Latency $=9\mathrm{.}3ns,$ Maximum data input frequency $=107MHz$

Pipelined:

Latency $=16\mathrm{.}5ns,$ Maximum data input frequency $=625MHz$

Unpipelined:

Latency $=11\mathrm{.}8ns,$ Maximum data input frequency $=84MHz$

Pipelined:

Latency $=16\mathrm{.}5ns,$ Maximum data input frequency $=303MHz$

Unpipelined:

Latency $=11\mathrm{.}8ns,$ Maximum data input frequency $=84MHz$

Pipelined:

Latency $=13\mathrm{.}2ns,$ Maximum data input frequency $=303MHz$