PLEASE ANSWER ALL PARTS FOR PROBLEM 1

(40%) Problem 1: Point out the types of VHDL statements below: ( 4 x 10 - 40%) (1) A B and C or D after 10 ns; Concurrent Sequential (2) Wait on AT': : Concurrent Sequential (3) If(A='1') Then B "0001" ENDIF "" ENDIF Concurrent concurent Sequential (4) With A select "001" when "01", Concurrent "111" when "11, C="000" when others; Sequential (5) A:= 101.6; B :* A+1; Concurrent concurrent sequential (6) U1: AND_3 PORT MAP ( X, Y, '0') Concurrent Sequential (7) Process begin A :=B+1; end process Concurrent Sequential (8) Case A is when "00" => '0'; when others -> Report "error", (9) F-001" when A="11" else "111" when B = "00" Concurrent sequential (9) F="701" when A="1" eka 1 when = "0" (10) if n o 1o 5 loop end top concurent Concurrent sequential (10) If I in 0 to 5 loop ...end loop Concurrent Sequential