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2. For the given sequence of instructions, fill the table below with the pipeline stages for each instruction. IMPORTANT: ASSUME that due to a hardware defect ALU takes twice the time to MULT/DIV, also "forwarding, that is the result of BUS is available in the beginning of the next 2 clock cycles. If possible, try to reduce the number of cycles by changing the sequence of the code without altering the output. How many cycles does it take to execute his piece of code? "You might need more clock cycles