please answer as soon as possible it is urgent.

2. [20pts] Multiple choice questions. Each question has at least one correct answer; some may have more than one correct answer. Mark all the correct answers to get full points. Partial credits will be given only if no incorrect answers are chosen. Marking an incorrect answer results zero point in the question, so do NOT guess. (4 pts per question) a. Which of the following statement is true about cache design trade-offs? i. Increasing associativity improves cache access time ii. Increasing cache block size reduces cache miss penalty iii. Increasing cache size improves cache hit rates iv. Increasing cache size reduces capacity misses b. Which of the following statements is not true? i. Pipelining takes advantage of instruction level parallelism. ii. Page faults are handled by the operating system. iii. For a virtual memory system with 48 -bit virtual addresses, a single page table and 4KB physical page size, the width of the virtual page number portion of an address is 34 bits. iv.A CPU with a faster clock frequency always has higher performance than one with a slower clock. c. Which of the following makes parallel programming difficult? i. Limited amount of parallelism available in programs/algorithms ii. Number of available processors iii. Partitioning and coordination overhead iv. Memory hierarchy Sol: d. Which of the following statement is true about data dependencies in the code below? I1: 1 Wh $2,0($1) I2: 1wh $1,40($6) I3: sub $6,$1,$2 I4: add $6,$2,$2 1. 12 depends on 11 ii. 13 depends on 11 e. Which of these things might happen in the code below? i. A NOP is required to avoid data hazards. ii. Forwarding between EX/MEM and ID/EX will occur. iii. Forwarding between MEM/WB and ID/EX will occur. 4 Name: iv. The pipeline might be flushed