please answer that question right with right steps For the given simplified circuit structure containing $5$ key functional blocks $($A$-$E$),$ with individual

propagation delays $($shown within each block$)$ determine the Latency and approximate maxlmum

data Input frequency for the circuit $($Unplpllned$)$ and if the circuit was appropriately PIpellned.

Unpipelined:

Latency $=9\mathrm{.}3ns,$ Maximum data input frequency $=107MHz$

Pipelined:

Latency $=13\mathrm{.}2ns,$ Maximum data input frequency $=303MHz$

Unpipelined:

Latency $=9\mathrm{.}3ns,$ Maximum data input frequency $=107MHz$

Pipelined:

Latency $=16\mathrm{.}5ns,$ Maximum data input frequency $=625MHz$

Unpipelined:

Latency $=11\mathrm{.}8ns,$ Maximum data input frequency $=84MHz$

Pipelined:

Latency $=16\mathrm{.}5ns,$ Maximum data input frequency $=303MHz$

Unpipelined:

Latency $=11\mathrm{.}8ns,$ Maximum data input frequency $=84MHz$

Pipelined:

Latency $=13\mathrm{.}2ns,$ Maximum data input frequency $=303MHz$