Please answer the quesitons below:

$9.$ Now we consider that the working of a pipelined processor, with the normal $5-$step pipeline discussed in class. $($Instruction Fetch $/$ Decode $/$ Execute $/$ Mem $/$ Writeback.$)$

n instructions will in the ideal case $($no hazards$)$ take n$+4$ cycles to complete. However, we actually were given this code to run:

add $s$1,$ $s$2,$ $s$3$ #$1$

lw $s$3,0($$s$1)$ #$2$

add $s$2,$ $s$2,$ $s$3$ #$3$

add $s$3,$ $s$1,$ $s$2$ #$4$

This is not the ideal case. Why not $$ can you spot the hazard? How long will the code take to run $($assuming no smart solutions such as bypassing etc.$)?$ Could this have been remedied with creative reordering of the instructions?

$10.$ In class, we discussed a processor that takes $800$ ps for a clock cycle. When $5-$stage pipelined, the processor required $200$ ps for a clock cycle. How much was the slowdown in latency, and why did it happen?

$($Hint: not every sub$-$step needed $200$ ps$,$ register read$/$write needed $100,$ but all steps were made the same length to fit. Flesh out the details.$)$

Despite the increased latency, the pipeline executes a long sequence of instructions faster than the single$-$cycle design. Explain why, and how much speedup we get in the ideal case. Given $20\%1-$cycle instructions, $25\%2-$cycle, $30\%3-$cycle, $5\%4-$cycle, and $20\%5-$cycle. What is the average CPI, and how fast $($in million instructions per second$)$ will the processor run this program? Answer for both the single$-$cycle and the pipelined version.