Please complete the following chart with the information given:

This project consists of design, simulations, and analysis of low$-$dropout regulator. Requirements:

Voltage supply $2\mathrm{.}5$ V $,$ CMOS TSMC $0\mathrm{.}3m$ Process

$V_{\text{R}\text{E}\text{F}}=1\mathrm{.}25V$

Output capacitor $=80pF$

Delivers $0\mathrm{.}3mA100mA$ current

Output Regulated Voltage of

LDO Simulations:

Complete the overall system. Ignore $C_1$ and use current source to represent $i_L$ load. Pick $R_1$ and $R_2$ to get $1\mathrm{.}25$ V at the feedback input.

Open loop:

a$)$ DC analysis:

Generate a table to report DC operating points of the Circuit at $0\mathrm{.}3mA,1mA,10$ mA and $100$ mA load condition.