Question: Please complete the GenClock.vhd and TestClock.vhd VHDL files to simulate this clock program. The GenClock.vhd and TestClock.vhd templates are already given, they just must be

Please complete the GenClock.vhd and TestClock.vhd VHDL files to simulate this clock program. The GenClock.vhd and TestClock.vhd templates are already given, they just must be completed. The constraint.xdc file is already given to you at the bottom. Beneath the templates is a hint diagram for how the code should flow. I will be sure to upvote.

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