Please complete the two sections of verilog code and a diagram that is asked in the tasks below, thank you.

Laboratory 5 Finite State Machines Prelab 1) complete all Verilog files 2) compile your designs 3) simulations(optional) Obiectives 1) Design basic and timed FSMs 2) Understand the behavior of FSMs Partl a basic Moore FSM Circuit description We will design a game on a 7-segment display (SSD). The diagram is shown in Fig.1 HEX0[0:6] clk 1 CLOCK 50 fsml _| clock KEY[O] Fig.1 The diagram of a SSD game. The first module clock generates a 1 Hz clock signal, clk i, from a 50MHz clock signal, CLOCK_50. With clk 1 as clock input and KEYI0] as reset, module fsml delivers HEX0[0:6] to drive a 7-segment display on DE2 board. The LEDs in the 7-seg display are turned on according to the following sequence: moves around in a clockwise direction. Sometimes a single LED is turned on, and sometimes two LEDs are turned on. In either case, LED(s) is on for 1 second. Laboratory 5 Finite State Machines Prelab 1) complete all Verilog files 2) compile your designs 3) simulations(optional) Obiectives 1) Design basic and timed FSMs 2) Understand the behavior of FSMs Partl a basic Moore FSM Circuit description We will design a game on a 7-segment display (SSD). The diagram is shown in Fig.1 HEX0[0:6] clk 1 CLOCK 50 fsml _| clock KEY[O] Fig.1 The diagram of a SSD game. The first module clock generates a 1 Hz clock signal, clk i, from a 50MHz clock signal, CLOCK_50. With clk 1 as clock input and KEYI0] as reset, module fsml delivers HEX0[0:6] to drive a 7-segment display on DE2 board. The LEDs in the 7-seg display are turned on according to the following sequence: moves around in a clockwise direction. Sometimes a single LED is turned on, and sometimes two LEDs are turned on. In either case, LED(s) is on for 1 second