Please complete this in LOGIC, NOT HDL

*This is all I was given from textbook; professor wants it done in logic instead of HDL

5.54 A synchronous Moore machine has two inputs x1 and x2, and an output y_out. If both inputs have the same value, the output is asserted for one cycle; otherwise, the output is 0. Develop a state diagram and a write an HDL behavioral model of the machine. Demon- strate that the machine operates correctly