Please convert the following Verilog code with testbench from $6$th order to $8$th order, and from $4-$bit word size to $8-$bit word size. Thank you!

module FIR$\_$pipeline $($ FIR$\_$A$,$ FIR$\_$B$,$ FIR$\_$C$,$ Sample$\_$in$,$ clock, reset$)$;

parameter FIR$\_$order $=6$;

parameter sample$\_$size $=4$; $//$ maximum sample value is $15$

parameter weight$\_$size $=4$; $//$ maximum value may be $15$

parameter word$\_$size$\_$out $=11$; $//$ log$2(15*15*7)$

$//$output $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$assign;

output $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$A;

output $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$B;

output $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$C;

input $[$sample$\_$size $-1$: $0]$ Sample$\_$in;

input clock, reset;

FIR$\_$pipeline$\_$none U$1($FIR$\_$A$,$ Sample$\_$in$,$ clock, reset$)$;

FIR$\_$pipeline$\_$multiplier U$2($FIR$\_$B$,$ Sample$\_$in$,$ clock, reset$)$;

FIR$\_$pipeline$\_3$adders U$3($FIR$\_$C$,$ sample$\_$in$,$ clock, reset$)$;

endmodule

module FIR$\_$pipeline$\_$multiplier $($FIR$\_$out, Sample$\_$in$,$ clock, reset$)$;

parameter FIR$\_$order $=6$;

parameter sample$\_$size $=4$; $//$ maximum sample value is $15$

parameter weight$\_$size $=4$; $//$ maximum value may be $15$

parameter word$\_$size$\_$out $=11$; $//$ Tog$2(2^4*2^4*($order$+1))$

parameter product$\_$size $=$ sample$\_$size$+$weight$\_$size;

output reg $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$out;

input $[$sample$\_$size $-1$: $0]$ Sample$\_$in;

input clock, reset;

wire $[$weight$\_$size $-1$: $0]$ coefficients $[0$: FIR$\_$order$]$;

$//$ Filter coefficients

parameter b$0=4\text{'}$d$2$; assign coefficients $[0]=$ b$0$;

parameter b$1=4\text{'}$d$5$; assign coefficients $[1]=$ b$1$;

parameter b$2=4\text{'}$d$9$; assign coefficients $[2]=$ b$2$;

parameter b$3=4\text{'}$d$14$; assign coefficients $[3]=$ b$3$;

parameter b$4=4\text{'}$d$9$; assign coefficients $[4]=$ b$4$;

parameter b$5=4\text{'}$d$5$; assign coefficients $[5]=$ b$5$;

parameter b$6=4\text{'}$d$2$; assign coefficients $[6]=$ b$6$;

reg $[$sample$\_$size $-1$ : $0]$ Sample$\_$Array $[1$: FIR$\_$order$]$; $//7$th coefficient multiplied by Data$\_$in

integer k$,$ n;

reg $[$product$\_$size $-1$: $0]$ PR $[0$: FIR$\_$order$]$; $//$ Array format

always @$($posedge clock$)$

if $($reset $==1)$ begin

$//$ The input shift register

for $($k $=1$; k $<=$ FIR$\_$order; k $=$ k$+1)//$ to save on code lines

$//$ The pipeline register

for $($k $=0$; k $<=$ FIR$\_$order; k $=$ k$+1)//$ to save on code lines

PR$[$k$]<=0$;

$//$ The output register

FIR$\_$out $<=0$;

end

else begin

$//$ The input shift register

Sample$\_$Array $[1]<=$ Sample$\_$in;

for $($k $=2$; k $<=$ FIR$\_$order; k $=$ k$+1)$

Sample$\_$Array$[$k$]<=$ Sample$\_$Array$[$k$-1]$;

$//$ The Pipeline Register

PR$[0]<=$ coefficients $[0]*$ Sample$\_$in;

for $($n $=1$; n$<=$ FIR$\_$order; n $=$ n$+1)$

PR$[$n$]<=$ coefficients $[$n$]*$ Sample$\_$Array$[$n$]$;

$//$ The output register

FIR$\_$out $<=$PR$[0]+$ PR$[1]+$ PR$[2]+$ PR$[3]+$ PR$[4]+$ PR$[5]+$ PR$[6]$;

end

endmodule

module FIR$\_$pipeline$\_$tb $()$;

parameter FIR$\_$order $=8$;

parameter sample$\_$size $=8$;

parameter weight$\_$size $=8$;

parameter word$\_$size$\_$out $=$ sample$\_$size $+$ weight$\_$size $+3$;

parameter product$\_$size $=$ sample$\_$size $+$ weight$\_$size;

wire $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$A;

wire $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$B;

wire $[$word$\_$size$\_$out $-1$: $0]$ FIR$\_$C;

reg $[$sample$\_$size $-1$: $0]$ Sample$\_$in;

reg clock, reset;

FIR$\_$pipeline UUT $($ FIR$\_$A$,$ FIR$\_$B$,$ FIR$\_$C$,$ Sample$\_$in$,$ clock, reset$)$;

wire $[$product$\_$size $-1$: $0]$ PR$0$; assign PRO $=$ UUT.U$2.$PR$[0]$;

wire $[$product$\_$size $-1$: $0]$ PR$1$; assign PR$1=$ UUT.U$2.$PR$[1]$;

wire $[$product$\_$size $-1$: $0]$ PR$2$; assign PR$2=$ UUT.U$2.$PR$[2]$;

wire $[$product$\_$size $-1$: $0]$ PR$3$; assign PR$3=$ UUT.U$2.$PR$[3]$;

wire $[$product$\_$size $-1$: $0]$ PR$4$; assign PR$4=$ UUT.U$2.$PR$[4]$;

wire $[$product$\_$size $-1$: $0]$ PR$5$; assign PR$5=$ UUT.U$2.$PR$[5]$;

wire $[$product$\_$size $-1$: $0]$ PR$6$; assign PR$6=$ UUT.U$2.$PR$[6]$;

$//$ Probes to observe the pipleine register PR$0$ at the input of adder $1$

wire $[$product$\_$size $-1$: $0]$ PR$00$; assign PR$00=$ UUT.U$3.$PR$[0]$;

wire $[$product$\_$size $-1$: $0]$ PR$01$; assign PR$01=$ UUT.U$3.$PR$[1]$;

wire $[$product$\_$size $-1$: $0]$ PR$02$; assign PR$02=$ UUT.U$3.$PR$[2]$;

wire $[$product$\_$size $-1$: $0]$ PR$03$; assign PR$03=$ UUT.U$3.$PR$[3]$;

wire $[$product$\_$size $-1$: $0]$ PR$04$; assign PR$04=$ UUT.U$3.$PR$[4]$;

wire $[$product$\_$size $-1$: $0]$ PR$05$; assign PR$05=$ UUT.U$3.$PR$[5]$;

wire $[$product$\_$size $-1$: $0]$ PR$06$; assign PR$06=$ UUT.U$3.$PR$[6]$;

$//$ Probes to observe the pipleine register PR$1$ at the input of adder $3$

wire $[$product$\_$size $-1$: $0]$ PR$12$; assign PR$12=$ UUT.U$3.$PR$[2]$;

wire $[$product$\_$size $-1$: $0]$ PR$13$; assign PR$13=$ UUT.U$3.$PR$[3]$;

wire $[$product$\_$size $-1$: $0]$ PR$14$; assign PR$14=$ UUT.U$3.$PR$[4]$;

wire $[$product$\_$size $-1$: $0]$ PR$15$; assign PR$15=$ UUT.U$3.$PR$[5]$;

wire $[$product$\_$size $-1$: $0]$ PR$16$; assign PR$16=$ UUT.U$3.$PR$[6]$;

$//$ Probes to observe the pipleine register PR$2$ at the input of adder $5$

wire $[$product$\_$size $-1$: $0]$ PR$24$; assign PR$24=$ UUT.U$3.$PR$[4]$;

wire $[$product$\_$size $-1$: $0]$ PR$25$; assign PR$25=$ UUT.U$3.$PR$[5]$;

wire $[$product$\_$size $-1$: $0]$ PR$26$; assign PR$26=$ UUT.U$3.$PR$[6]$;

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