Please create a RICS based program in logisim$.$ Please follow the given instructions. Program Counter Design

The Program Register $($PR$)$ is

inside the Program Counter $($PC$)$

Its output will change it based on

feedback from the instruction

being executed

Set "trigger" to "falling edge" for

Program Register

PCMODE indicates whether to

INCREMENT, add the offset

IMMEDIATE, change it to

ABSOLUTE, or NO CHANGE

Example $($see inputs to MUX$)$:

$0=$ increment, $1=$ immediate,

$2=$absolute$,3=$no change Instruction Storage

The program instructions will be

stored into a ROM $(256$ x $12)$ for

this simple CPU

Each address holds a single

instruction

Variables will be stored in a

separate RAM to simplify the design

The address will be provided by the

Program Register $($PR$),$ which is in

the Program Counter $($PC$)$

component

The output will go to the instruction

decoder $($ID$)$

Encode data using hexadecimal

$($one digit is $4$ bits$)$ Instruction Decode $($Part $1)$

RISC design attempts to simplify instruction

decode $($ID$)$

Only wires!

Consistently place all instruction operands in the

same bits for all instruction types

Use "splitter" to break up busses into smaller

busses$/$wires or combine smaller busses$/$wires into

larger busses

Set "Bit Width In$"$ to $12,$ and "Fan Out" is the number

of taps coming out of the splitter

Set which taps as assigned to which bits

Use "tunnels" to make connecting wires easier

Instruction Decode $($Part $2)$

Need to use OPCODE, EXTRA, and ALUZERO to determine how to

execute instructions

Can use a Look$-$Up$-$Table $($LUT$)$ to determine proper outputs

Better than creating custom logic circuit $($remember the $7-$segment

decoder from DLD$1)$

Based on figure, LUT would be at least a $7$ bit input resulting in $128$ rows

Instead use Programmable Logic Array $($PLA$)$

Better than LUT as it can have $"x"$ in input patterns

Your input patterns will have $"x"$s in a number of places

Input signal to the PLA must not contain $"x"$s$,$ or the output will be $"x\text{'}$s$"$

This CPU will only have $13$ PLA rows

The rows can be in any order $-$ the order is not important

PLA$-$OUT will be split up to drive control signals of the remaining

circuit

Can not have $"x"$s in outputs, must set to something $-$ see specifications

Reserve $3$ bits for EXTRA in PLA $($it is currently $2,$ set higher bit to

$"0"$ for now$)$Register File Design

Able to read $2$ registers per clock

Set $"$R$1$IN$"$ for register to read $(0-3),$

output at $"$R$1$OUT"

Same for $"$R$2$IN$",$ and $"$R$2$OUT"

Able to write to one register per

clock

Apply data to "DATAIN"

Set "WINDEX" to register to write to

$(0-3)$

Goes through a decoder $($with enable;

all outputs set to $0$ on disabled$)$

Set "WENABLE" to $1$ to write

No $"$r$0"$; hard set to $0$ at output MUX

Set "trigger" to "falling edge" for

registers

ALU Design

Build your own ALU

Based heavily on Register File

Have a single MUX just before output

ALUOP should be $3$ bits $($for expansion$),$

$8$ total modes possible

$"$O$1$IN$"$ is register value of RS$,$ and

$"$O$2$IN$"$ is register value of RT

Three modes necessary $($for now$)$:

Add: ALUOUT$=$O$1$IN$+$O$2$IN

Subtract: ALUOUT$=$O$1$IN$-$O$2$IN

Borrow: ALUOUT$=1$ if O$2$IN$>$O$1$IN$,$ otherwise $0$

Take $"$b out" from subtractor above, extend to $4$ bits with ZERO extension

ALUZERO output should be high if ALUOUT is zero $($use a comparator$)$

For example: ALUOP is $0$ for ADD, $1$ for SUBTRACT, and $2$ for BORROW