Question: Please design a 2 - stage logic micro - operations circuit using J - K flip - flops using the imaged logic operations. Include a

Please design a 2- stage logic micro-operations circuit using J-K flip-flops using the imaged logic operations. Include a drawing of the circuit, including all work done to derive the circuit, including any relevant tables and k - maps.
The first micro-operation, Ai - Ai V Bi' is a nameless micro-operation the boolean function F11=x+y'
The second micro-operation, Ai - Ai'\Lambda Bi is a nameless micro-operation, with the boolean function F4=x'y
The third micro-operation, Ai -(Ai V Bi)' is the NOR micro-operation, with the boolean fuction F8=(x+y)'
The fourth micro-operation, Ai -(Ai \Lambda Bi)' the NAND micro-operation, with the boolean function F14=(xy)'
The fifth micro-operation, Ai - Ai Bi is the XOR micro-operation, with the boolean function F6= X Y
The fifth micro-operation, XOR, can be implemented/wired by connecting input pins Bi and another input pin into the inputs of an AND, and connecting the output of the AND into both J and K inputs of a JK flip-flop, connecting the output Q into output bit Ai. A clock pin goes into the clock input of the JK flip-flop. I am not sure how the other micro-operations are wired.
The flip-flop state table for XOR is as follows
|PS | INPUT | NEXT STATE | FF INPUTS|
|Ai | Bi | Ai | JAi KAi |
----------------------
|0|0|0|0 x |
|0|1|1|1 x |
|1|0|1| x 0|
|1|1|0| x 1|
The appropiate k-maps for XOR would be as follows
Ai\Bi|0|1|
0|0|1|
1|x}x|
JAi=Bi
Ai\Bi|0|1|
0|x|x|
1|1|1|
KAi=Bi
Such tables and k-maps for all micro-operations are required. Please refer to a truth table and excitation table of the JK flip-flop if needed.
For the two-stage circuit, create one circuit with input B0 and output A0, and another circuit with input B1 and output A1. Both will have a common set of T inputs. I believe the circuit might use a single JK flip-flop, but I am not certain.
 Please design a 2- stage logic micro-operations circuit using J-K flip-flops

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