Please design a computational system whose transfer function is defined as follows. A series of 8-bit...

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Please design a computational system whose transfer function is defined as follows. A series of 8-bit positive integer is generated as the input of the computational system by the test bench. The output value Y is a 10-bit positive integer, which is calculated according to equations (1), (2), (3) and (4). |5j+n-1 21-1 Xavg, = where Xi is the value of the ith input data and j>=1. .n-9 in this homework XS = {X₁, X₁+1, X₁+2, Xj+n-1}.. Xappr, Xavg, if Xavg, EXS = {(x₁1 (X, EXS) (X₁1 (X₁ € XS) and (X₁ < Xave,) and (Xave, - X, is minimal) if Xavg, #XS" Xappr = where Xappr, is the value of the jth approximate average 12-¹(x₁+Xappr M-1 ,where y, is the value of the jth output data. (1) 2 The computational system produces the output sequence according to the given input sequence. Each input and output data in the respective sequence is indexed. This index, in terms of hardware, is the relative time when the input data is given or the output data is ready. Thinking as a hardware designer, the approximate average is chosen from the last n input data which should be stored in the system. The system should be able to calculate the integral part of the real average of the last n input data first. And then if the integral part of the real average equals to any one of the last n input data, the approximate average is simply the integral part. Else the approximate average is the one which is one of the last n input data whose value is smaller than and closest to the integral part of the real average. The above descriptions stated the desired operations as those defined by equations (1), (2), and (3). After the approximate average is obtained, the output value can be calculated according to equation (4). First, the last / input value is added by the corresponding approximate average. And then they are summed up and divided by n-1. The output value is the quotient after division. For example, assume that n-4, X-3, X-24, X=16, X-8, and X-3. After the first 5 input items are given, the system should store them and calculate the output value. The average of the first 4 input values is 12(only the integral part is left). Since it is not in the set of {X1, X2, X3, X+), the system selects one from {X1, X2, X3, X4} as the approximate average whose value is smaller than 12 and close to 12. In this case, the approximate average is 8. So the first output value is calculated n as [[(3 + 8) + (24+8) + (16+8) + (8 + 8)] / [(4-1)]]= 27. Similar to those described above, when the 5th input data item is given, the system should store X., X₁, X, and X, and calculate the corresponding output value. The 2nd output value should be the same as the first one because the values stored in the system is the same. Design Specifications a. Block Overview b. I/O Interface clk Signal Name I/O width clk I 1 reset X reset c. Timing Diagrams Test Bench X Y I I 0 Teycle -Tresor X₁ 1 8 10 clk reset X 10 Computational System Description clock for the computational system reset the state of the computational system when it asserts input data of the computational system computed output X₂ X₂ X10 X₁1 XXXXXXXXXXXXXXXXXXXXXXXXX d. File Description File Name CS.V testfixture.v in.dat out golden.dat M Start Simulation Design | VHOL Verlog | Löbraries | SOF | Others | Pulse Options Other Options Scoring a. Functional Simulation (pre-sim) [100%] All of the result should be generated correctly, and you will get the following message in ModleSim simulation. You can turn off the timing check in presim only??. Disable pulse error and warning messages(+no_pulse_msg) Rejection Limit ErrorL % (pulse) Enable hazard checking-hazards) Disable timing checks in specify blocks(+natingcheck) User Defined Arguments (+<plusarg>) % (+puse_) Description RTL code for using Verilog Test bench for verifying design Input patterns Golden output patterns Delay Selection default X Cancel Please design a computational system whose transfer function is defined as follows. A series of 8-bit positive integer is generated as the input of the computational system by the test bench. The output value Y is a 10-bit positive integer, which is calculated according to equations (1), (2), (3) and (4). |5j+n-1 21-1 Xavg, = where Xi is the value of the ith input data and j>=1. .n-9 in this homework XS = {X₁, X₁+1, X₁+2, Xj+n-1}.. Xappr, Xavg, if Xavg, EXS = {(x₁1 (X, EXS) (X₁1 (X₁ € XS) and (X₁ < Xave,) and (Xave, - X, is minimal) if Xavg, #XS" Xappr = where Xappr, is the value of the jth approximate average 12-¹(x₁+Xappr M-1 ,where y, is the value of the jth output data. (1) 2 The computational system produces the output sequence according to the given input sequence. Each input and output data in the respective sequence is indexed. This index, in terms of hardware, is the relative time when the input data is given or the output data is ready. Thinking as a hardware designer, the approximate average is chosen from the last n input data which should be stored in the system. The system should be able to calculate the integral part of the real average of the last n input data first. And then if the integral part of the real average equals to any one of the last n input data, the approximate average is simply the integral part. Else the approximate average is the one which is one of the last n input data whose value is smaller than and closest to the integral part of the real average. The above descriptions stated the desired operations as those defined by equations (1), (2), and (3). After the approximate average is obtained, the output value can be calculated according to equation (4). First, the last / input value is added by the corresponding approximate average. And then they are summed up and divided by n-1. The output value is the quotient after division. For example, assume that n-4, X-3, X-24, X=16, X-8, and X-3. After the first 5 input items are given, the system should store them and calculate the output value. The average of the first 4 input values is 12(only the integral part is left). Since it is not in the set of {X1, X2, X3, X+), the system selects one from {X1, X2, X3, X4} as the approximate average whose value is smaller than 12 and close to 12. In this case, the approximate average is 8. So the first output value is calculated n as [[(3 + 8) + (24+8) + (16+8) + (8 + 8)] / [(4-1)]]= 27. Similar to those described above, when the 5th input data item is given, the system should store X., X₁, X, and X, and calculate the corresponding output value. The 2nd output value should be the same as the first one because the values stored in the system is the same. Design Specifications a. Block Overview b. I/O Interface clk Signal Name I/O width clk I 1 reset X reset c. Timing Diagrams Test Bench X Y I I 0 Teycle -Tresor X₁ 1 8 10 clk reset X 10 Computational System Description clock for the computational system reset the state of the computational system when it asserts input data of the computational system computed output X₂ X₂ X10 X₁1 XXXXXXXXXXXXXXXXXXXXXXXXX d. File Description File Name CS.V testfixture.v in.dat out golden.dat M Start Simulation Design | VHOL Verlog | Löbraries | SOF | Others | Pulse Options Other Options Scoring a. Functional Simulation (pre-sim) [100%] All of the result should be generated correctly, and you will get the following message in ModleSim simulation. You can turn off the timing check in presim only??. Disable pulse error and warning messages(+no_pulse_msg) Rejection Limit ErrorL % (pulse) Enable hazard checking-hazards) Disable timing checks in specify blocks(+natingcheck) User Defined Arguments (+<plusarg>) % (+puse_) Description RTL code for using Verilog Test bench for verifying design Input patterns Golden output patterns Delay Selection default X Cancel

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Polymorphic types in functional programming allow variables functions or data structures to operate on values of different types They provide flexibil... View the full answer