Please design the entity as well as the test bench for this combinational circuit. In your design, please set up internal signals A$1,$ B$1,$ A$2,$ B$2,$ A$3,$ B$3,$ A$4,$ B$4,$ A$5,$ B$5,$ A$6,$ B$6,$ A$7$ and B$7.$

Your entity design is:

Your test bench design is:

In your test bench design, please let L$0,$ L$1,$ L$2,$ L$3$ to go through $"0000","0001","0010",0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,"1110","1111",$ each at a period of $100ns.$ Do this for COMP $=\text{'}0\text{'}$ first, and then let COMP $=\text{'}1\text{'}.$