PLEASE DO ALL PARTS

Consider the multi-cycle processor shown in the following figure. For each instruction and the stage of execution provided, show which control signals are used and what are their corresponding values. [Note: For the control signals you do not list for each answer, we will assume them to be 0 if they are critical signals for the given stage; and the critical ones will be taken as don't-cares.] CWrite Outputs MemRead Control MemWrite Op RogWrite ddress 31-02 26 Shit et 2 28 31-26) (25-211 20-16 15-0 InstructionuWrite PC [31-28) PC Read register 1 Read Address Reed data 1A U register 2 Zero ALU ALU MemData Instruction Registers ALUOut Write data 2B Instruction15-11register Read 15-0) Sign 32 extend ALU Shift left 2 register Instruction 15-41 (a) beq r1, $r3, loop IF stage (b) sw $t1, 4($t0) ID stage (c) j target - Completion stage (d) lw $to, 4096($r3) MEM stage (e) slt $r1, $r2, $r3 - WB stage Consider the multi-cycle processor shown in the following figure. For each instruction and the stage of execution provided, show which control signals are used and what are their corresponding values. [Note: For the control signals you do not list for each answer, we will assume them to be 0 if they are critical signals for the given stage; and the critical ones will be taken as don't-cares.] CWrite Outputs MemRead Control MemWrite Op RogWrite ddress 31-02 26 Shit et 2 28 31-26) (25-211 20-16 15-0 InstructionuWrite PC [31-28) PC Read register 1 Read Address Reed data 1A U register 2 Zero ALU ALU MemData Instruction Registers ALUOut Write data 2B Instruction15-11register Read 15-0) Sign 32 extend ALU Shift left 2 register Instruction 15-41 (a) beq r1, $r3, loop IF stage (b) sw $t1, 4($t0) ID stage (c) j target - Completion stage (d) lw $to, 4096($r3) MEM stage (e) slt $r1, $r2, $r3 - WB stage