PLEASE DO NOT COPY PASTE FROM CHEGG/OTHERWISE I'LL REPORT YOU

QUESTION:4 System of Cache A Figure 1 depicts a section of the caching system A. The system is byte addressable, with a one-word block size (4 bytes). Binary numbers are used to express the tag and line number. Hexadecimal is used to express the contents of words in block. 00 01 10 11 10 1000 0100 1001 0110 1101 2016 6116 Clus 2116 10 1000 0100 1001 0110 1110 326 7216 C216 0216 10 1000 0100 1001 A21 0110 1111 4216 8216 4116 10 1000 0100 1101 0111 0000 5216 9216 521 B24 0110 1111 4216 8216 4116 10 1000 0100 1101 0111 0000 5216 9216 521 B24 System B Cache A 2- way set-associative mapping cache system is represented by cache system B. The system is byte addressable, with a one-word block size (4 bytes). Binary numbers are used to express the tag and set number. Hexadecimal is used to express the contents of words in block. Tag 00 01 10 11 10 1000 0100 1001 0110 1101 2016 6116 C116 2116 11 1100 0100 1001 0110 1101 326 7216 026 0216 10 1000 0100 1001 0110 1110 4216 8216 4116 A216 11 1100 0100 1101 0110 1110 5216 926 8216 B216 10 1000 0100 1001 0110 1111 2016 6116 D116 5116 11 1100 0100 1001 0110 1111 325 725 C216 D 1. In a cache system, if we access memory in the following order, A. a. AIFF B8 D. B1 FF B8 C. A1 FF B3 d. B1 FF B8 e. A1 FF BS f. B1 FF B8 A. a. Al FF B8 b. B1 FF B8 What are the chances of a data request cache miss? 2. How many cache misses will occur if we access the above memory addresses in the Cache system B from