PLEASE DO NOT USE AI TOOLS LIKE CHATGPT TO ANSWER. Since your circuit handles only BCD digits, check for the cases when the input $x$ or $Y$ is greater than nine.

If this occurs, indicate an error by turning on the red light $LED{R}_9.$

Use ModelSim to simulate and debug your Verilog code. Make sure that you produce the correct output

values for all possible results of the BCD addition.

A top.v file is provided in the design files for this exercise, for use with the DESim tool. To use the top.v file

directly, declare your Verilog module as:

module part$4($SW$,$ LEDR, HEX$5,$ HEX$4,$ HEX$3,$ HEX$2,$ HEX$1,$ HEX$0)$;

input $[8$:$0]$ SW;

output $[9$:$0]$ LEDR;

output $[6$:$0]$ HEX$5,$ HEX$4,$ HEX$3,$ HEX$2,$ HEX$1,$ HEX$0$;

endmodule

After you have finished testing your Verilog code using simulation, create a new Quartus project for your

$BCD$ adder.

Include the necessary pin assignments for the DE$1-$SoC board, compile the circuit, and download it into the

FPGA chip.

Test your circuit by trying different values for numbers $x,Y,$ and $c_{in}.$ modu$1$e top $($CLOCK$\_50,$ SW$,$ KEY, HEX$0,$ HEX$1,$ HEX$2,$ HEX$3,$ HEX$4,$ HEX$5,$ LEDR$)$;

input CLOCK$\_50$; $//$ DE$-$series $50$ MHz clock signa$1$

input wire $[9$:$0]$ SW; $//$ DE$-$series switches

input wire $[3$:$0]$ KEY; $//$ DE$-$series pushbuttons

output wire $[6$:$0]$ HEXO; $//$ DE$-$series HEX displays

output wire $[6$:$0]$ HEX$1$;

output wire $[6$:$0]$ HEX$2$;

output wire $[6$:$0]$ HEX$3$;

output wire $[6$:$0]$ HEX$4$;

output wire $[6$:$0]$ HEX$5$;

output wire $[9$:$0]$ LEDR; $//$ DE$-$series LEDs

part$4$ U$1($SW$[8$:$0],$ LEDR, HEX$5,$ HEX$4,$ HEX$3,$ HEX$2,$ HEX$1,$ HEX$0)$;

endmodu$1$e

Part IV

For this part you are to design a circuit that has two decimal digits, $x$ and $Y,$ as inputs. Each decimal digit

is represented as a $4-$bit number. In technical literature this is referred to as the binary coded decimal $($BCD$)$

representation.

You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers $x$ and $Y,$

plus a carry$-$in$,c_{in}.$ When these inputs are added, the result will be a five$-$bit binary number. This result is to

be displayed on $7-$segment displays as a two$-$digit BCD sum $S_1{S}_0.$ For a sum equal to zero you would display

$S_1{S}_0=00,$ for a sum of one $S_1{S}_0=01,$ for nine $S_1{S}_0=09,$ for ten $S_1{S}_0=10,$ and so on$.$ Note that the

inputs $x$ and $Y$ are assumed to be decimal digits, which means that the largest sum that needs to be handled by

this circuit is $S_1{S}_0=9+9+1=19.$

Perform the steps given below.

Write Verilog code for the BCD adder. You must use only simple assign statements to specify the required

logic functions$-$do not use other types of Verilog statements such as if$-$else or case statements for this part

of the exercise. One reasonable approach in designing this circuit is to use a modified version of the solution

for Part II$.$ In that part you had to display a four$-$bit number on the $7-$segment displays. In this part you have

to make a five$-$digit number by adding $x+Y,$ and display that on the $7-$segment displays. The five$-$bit

sums $0$ to $15$ would already "just work" using the approach from Part II$.$ But for sums $16,17,18,$ and $19$

you would not directly display $z($see Figure $1)$ on HEX$1$ and $M$ on HEX$0.$ Instead, for these sums $($which

are the sums for which the carry$-$out of $x+Y$ is $1)$ you would have to provide different signals for the

$7-$segment decoders. Alternatively, there is a circuit in the recommended textbook that you could study,

understand $($so that you can explain it to your TA$!),$ and use.

Use switches $S{W}_{7-4}$ and $S{W}_{3-0}$ for the inputs $x$ and $Y,$ respectively, and use $S{W}_8$ for the carry$-$in$.$

Connect the five$-$bit result produced by your circuit to the red lights LEDR. Display the BCD values of $x$

and $Y$ on the $7-$segment displays HEX$5$ and HEX$3,$ and display the result $S_1{S}_0$ on HEXI and HEXO.