Please dont type c++codes, answer for question 1,2,3,4.

In this assignment you will design hardwired control to implement indexed addressing. An instruction using indexed addressing has an offset, which is added to the index register value in order to calculate the effective address (EA). Ex: ADD 100,X If index register IX contains 50,EA is calculated as 150 . EA+ offset +IX You will design an "Indexed" stage in the instruction execution cycle that calculates EA. Assume that the microoperations in the fetch cycle are as follows: PQt0:MARPCPQtl:MBRMemory,PCPC+1PQt2:1RMBR In the Indexed cycle, effective address must be calculated. At the end of the indexed cycle, effective address must be stored to the address field of the instruction register (IR(addr)), so that the same execute routines can be used. Ex: ADD100,X IR after Fetch cycle: opcode addr \begin{tabular}{|c|c|} \hline ADD & 100 \\ \hline \end{tabular} Index register IX contains: 50 Effective address calculation in Indexed stage: ER IR (addI) + IX Then, effective address is placed in IR (addr) IR after Indexed cycle: 1. Write the microoperations in the Indexed cycle to implement indexed addressing. 2. Write the conditions for each microperation. Assume that in the indexed cycle PQ11. 3. Draw the circuit for hardwired control. Assume that the bus select logic selects the registers for the bus according to the following table. 4. Write the microcode for Indexed cycle. Assume that in the control memory, starting address of the Indexed cycle is 0100100 . Use the microoperations on the next page