Please explian answer. I will thumbs up

10. 15 points) A RISC processor executes the following code. There are data dependencies but no internal forwarding. A source operand cannot be used until it has been written. ADD r0, rl, r2 ADD r3, r6, r4 ADD r5, r3, r0 ADD 7, r0, r8 ADD r9, r6, r9 ADD r0, r3, r5 a. Assuming a four-stage pipeline (fetch, operand fetch, execute, and result write), what registers are being read during the eighth clock cycle and what register is being written? b. How long will it take to execute the entire sequence