Please fill in the question marks in the Verilog code!

Fill out the places vith the question mark! ladder 4B1t in. X out input Cin: nput 22???: input [2:0] Y: output22?: wire 22222,Cl; 'assign S[0] X01Y[01 Cin; ??22? sian Cout ?22 endmodule Fill out the places vith the question mark! module testbench reg Cin_t; ??22222 wire Cout t: 2222 UUT ( .Cin (Cint), ???2 initial begin end : always #5 clk = ~clk; 2???2 always #30 Y-t [1] -Y-t [1]; # endmodule