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Assume that the input logic of the microprogram sequencer of Fig. has four inputs, 12, /1,0, T (test), and three outputs, S1, S0, and L. The operations that are performed in the unit are listed in the following table. Design the input logic circuit using a minimum number of gates 210 Operation 000Increment CAR if T 1, jump to AD if T-0 x01Jump to AD unconditionally 100 Increment CAR unconditionally 0 | 1 | 0 | Jump to AD if T= 1, increment CAR if T = 0 110 Call subroutine if T 1, increment CAR if T 0 011Return from subroutine unconditionally 1 11Map external address unconditionally Figure Microprogram sequencer for a control memory (MAP) 0 Load MUX SBR MUx2 Test Clock-CAR Coneol memay