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Lab 7: More Sequential Circuit Analysis and Design PURPOSE The purpose of this lab is to design and simulate a simple sequential logic circuit using flip-flops Consider a device with a single input IN and a single output UNLOCK. This device is a sequence detector. The output UNLOCK is to be asserted if and only if a secret 'code' is entered. The code is always considered to be over the last few inputs (depending on the length of the code). Thus, code overlap IS allowed. Correct codes are considered to be entered MSB to LSB. Thus, the first bit entered for the code 11000 would be 1' There are two versions of this device. The Moore version of this device considers only inputs that have been successfully read at a clock tick to be part of the code sequence. The Mealy version of this device considers the last (LSB) bit of the code to the CURRENT input - even before the clock event occurs. For the purposes of this laboratory, assume that all combinational logic gates have a minimum propagation delay (in nanoseconds) equal to the number of inputs to the device. Assume that the maximum propagation delay for all combinational logic gates is twice its minimum propagation delay. Thus, a 3-input AND gate would have a minimum propagation delay of 3ns and a maximum propagation delay of 6 ns For the purposes of this laboratory, all flip-flops should be assumed to have a minimum propagation delay of 6ns, a maximum propagation delay of l0ns, a setup time of 5ns, and a hold time of Ins .[2 points] Figure is a logic diagram of a sequence detector. What is the code sequence (or sequences!) that causes UNLOCK to be asserted?!? Is the device Mealy or Moore? What are the relevant timing characteristics necessary to use the overall device? Document your answers with equations, diagrams, tables, and other evidence to demonstrate and support your claims Lab 7: More Sequential Circuit Analysis and Design PURPOSE The purpose of this lab is to design and simulate a simple sequential logic circuit using flip-flops Consider a device with a single input IN and a single output UNLOCK. This device is a sequence detector. The output UNLOCK is to be asserted if and only if a secret 'code' is entered. The code is always considered to be over the last few inputs (depending on the length of the code). Thus, code overlap IS allowed. Correct codes are considered to be entered MSB to LSB. Thus, the first bit entered for the code 11000 would be 1' There are two versions of this device. The Moore version of this device considers only inputs that have been successfully read at a clock tick to be part of the code sequence. The Mealy version of this device considers the last (LSB) bit of the code to the CURRENT input - even before the clock event occurs. For the purposes of this laboratory, assume that all combinational logic gates have a minimum propagation delay (in nanoseconds) equal to the number of inputs to the device. Assume that the maximum propagation delay for all combinational logic gates is twice its minimum propagation delay. Thus, a 3-input AND gate would have a minimum propagation delay of 3ns and a maximum propagation delay of 6 ns For the purposes of this laboratory, all flip-flops should be assumed to have a minimum propagation delay of 6ns, a maximum propagation delay of l0ns, a setup time of 5ns, and a hold time of Ins .[2 points] Figure is a logic diagram of a sequence detector. What is the code sequence (or sequences!) that causes UNLOCK to be asserted?!? Is the device Mealy or Moore? What are the relevant timing characteristics necessary to use the overall device? Document your answers with equations, diagrams, tables, and other evidence to demonstrate and support your claims