Please help! VHDL

Problem The following input transactions occur in the simulation of the VHDL architecture below. Show all the transactions that will occur during the simulation. b Time Ons 0 0 10 ns 1 20 ns ARCHITECTURE first OF problem IS BEGIN PROCESS (a b) BEGIN IF a 0 THEN x b after 5 ns; ELSE x 'Z' after 2 ns END IF END PROCESS y a AND b; END ARCHITECTURE first; (Hint: y a AND b is equivalent to Process (a, b) a AND b, End PROCESS