Please help with my computer architecture assignment. Will give thumbs up!

Question 4. A timing diagram for instruction pipeline operation has successive instructions on the vertical axis, and time on the horizontal axis. Create a timing diagram that illustrates the execution of the following instructions using the standard MIPS stages. Place an 'X' in every cell occupied by an unused phase. [30 Points] lw $t2,12($s3) add $t0,$s 1,$s2 lw $t3,16($s3) add $t1,$t1,$t0 sw $t3,8($s1) add $t2.$t2,$t3