Please help with my hw, I will give thumbs up! This was all that was given to me.

Question 2. Consider individual stages of the datapath that have the following latencies: IF ID 2.5 ns EX 2 ns MEM 4 ns WB 1.5 ns 1 ns a. [6 points] What is the clock cycle time in a pipelined and non-pipelined processor? b. [7 points] What is the total latency of a Load Word instruction in a pipelined and a non-pipelined processor? C. Suppose the MEM stage is split into two separate stages, each with a latency of 2 ns. i. [4 points) How many stages will the new processor have? ii. [8 points] What is the total latency of a Load Word instruction in this new processor