please help with these 2 problems. Answer clearly and to the best you can!! Thanks.

Consider the CMOS circuit below, with three inputs V1, V2, and V3, and one output Vout. The source terminal of the PMOS at the upper right of the circuit is connected to a 5v voltage source, for which the voltage can assumed to be significantly greater than 0. The source terminals of the NMOS at the bottom are connected to ground (0 Voltage). Write the truth table for the circuit, using 0's and 1's to denote low voltage and high voltage inputs and outputs. This circuit implements one of the standard digital logic gates. Which gate does it implement? We want to design the "full adder" digital circuit, for which there are three inputs and two outputs. The inputs are denoted as A, B, and C. The outputs are denoted as "Sum" and "Carry. The "Sum" output should be 1 when only one of the three inputs is 1, or when all three inputs are 1. The "Carry" output should be 1 when at least two of the three inputs are one. Write the truth table for this circuit. Draw a digital logic gate implementation of the circuit. How many NMOS and PMOS transistors does your implementation require? Consider the CMOS circuit below, with three inputs V1, V2, and V3, and one output Vout. The source terminal of the PMOS at the upper right of the circuit is connected to a 5v voltage source, for which the voltage can assumed to be significantly greater than 0. The source terminals of the NMOS at the bottom are connected to ground (0 Voltage). Write the truth table for the circuit, using 0's and 1's to denote low voltage and high voltage inputs and outputs. This circuit implements one of the standard digital logic gates. Which gate does it implement? We want to design the "full adder" digital circuit, for which there are three inputs and two outputs. The inputs are denoted as A, B, and C. The outputs are denoted as "Sum" and "Carry. The "Sum" output should be 1 when only one of the three inputs is 1, or when all three inputs are 1. The "Carry" output should be 1 when at least two of the three inputs are one. Write the truth table for this circuit. Draw a digital logic gate implementation of the circuit. How many NMOS and PMOS transistors does your implementation require