please help with this.

Task In your group, design and simulate a synchronous Medium Scale Integrated (Mst) dogle circuit with D flip-flops (DFF). The MSI circuit is one of the following 8xl multiplexer . 38 decoder 1x demultiplexer 422 priority encoder 3-bit ripple curry adder 3-bit subtractor 8-bit parity generator The MSI circuit for your group has been assigned to you see the assignment grouping file) Steps to complete the assignment Design the MSI circuit manually in Quartus peine using basic or universal gates (do not instantiate the component as a block). Refer to notes online resources on how to obtain the logic circuit for the component The circuit inputs should be connected to input perts, while each output should be cotinected to DFF. All DFF should be comected to a common clock and reset. Do not design the DFF register using logic gates, bet simply instantiate the di component from the library (primite->orage->di. Perform the connections like the example below: -- Simulate the circuit for several values to verify come functionality. The input values (eg. A and B) should be assigned at the negative edge of the clock and the output (e.g. CO) should be monitored at the positive edge of the clock. Choose any suitable clock frequency for your simulation. Note that the DFF competent ses an active how reset, t.e. OC-O when rest Submission Fach group will need to submit a short report which consists of Title page with suitable heading groupsumber, members, section, etc. Description of your MSI logic circuit with black diagram gate schematic, etc. > Logic circuit design in Quartus Prime Waveform simulation results in Quartus Prime