Please I need help

1) Answer the following questions regarding the buses. a. The word size dictates the size of which bus(es)? Address, control, data? b. Of the address, control and data buses, which one(s) is(are) unidirectional with information always originating from the CPU? c. Of the address, control and data buses, which one is used in the fetch portion of the fetch- execute cycle to move the next instruction from memory to the CPU? d. What type(s) of information is sent over the control bus? a. 2) We have an 8Gx64 word addressable memory built using 512Mx32 RAM chips. Memory is addressed using low-order interleave. NOTE: 4Gx64 means 4G of words, each word is 64 bits. How many RAM chips are needed to make up memory? b. How many banks does memory have? How many bits are needed for a memory address? d. Of those bits from part c, which are used for the bank select, and which are used for the address in the bank? c. For questions 3-4, provide the full MARIE RTN for these new MARIE operations. Include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. X is a main memory address (the last 12 bits of the 16-bit instruction) and should be referenced as IR[11..0] in your RTN. 3) Swap X - this instruction swaps the datum at address X with the datum in the AC. To accomplish this, you need a temporary storage location, assume there is an additional data register in the CPU called R1 for this purpose. 4) LoadOnZero X - like Load X except that it only performs the operation if the AC's value is currently 0