please implement this to gate level..... just change the code so its different please in verilog

module full_adder (x,y,z,S,C);

input x,y,z;

output S,C;

not n1 (nX,x),

n2 (nY,y),

n3 (nZ,z);

nand nd1 (O1,nX,nY,z),

nd2 (O2,nX,y,nZ),

nd3 (O3,x,nY,nZ),

nd4 (O4,x,y,z),

nd5 (S,O1,O2,O3,O4),

//for the carry

nd6 (O5,x,y),

nd7 (O6,x,z),

nd8 (O7,y,z),

nd9 (C,O5,O6,O7);

endmodule