Please just answer the maximum frequency with specific steps, thanks!

Part I Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses four T-type flip-flops. The counter increments its value on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear signal low. You are to implement a 8-bit counter of this type. EnableT Q IQ ClockQ Clear Figure 1: A 4-bit counter. 1. Write a VHDL file that defines a 8-bit counter by using the structure depicted in Figure I. Your code should include a T flip-flop module that is instantiated 8 times to create the counter. Compile the circuit. How many logic elements (LEs) are used to implement your circuit? What is the maximum frequency, Fmar, at which your circuit can be operated