please provide a full explanation.

FIFO (5 pts.): Explain these with regards to below figure for FIFO. (a) Why do we need " n+1 " bits for the counter in FIFO? Which outputs get detected this way? (b) Draw a small example where the point (a) above helps detecting such outputs. (c) What is the purpose of having two "comparing circuits"? (d) Which signals cross the clock domains? How does the circuit solve possible metastability? (e) Explain how multi-signal clock domain crossing is resolved through FIFO