Please show all steps. Thank you!

Question 6: DMA optimization: Compute and compare CPU memory transfers with DMA transfers to an IO device. Reminder: bps bits/second; not bytes/second) A microcontroller has the following characteristics: . ARM Cortex, single cycle 80 MHz clock, with one clock per instruction for most cases Programmed data transfer takes 4 cycles per 32-bit word DMA transfer capability, transferring 32-bits per memory clock USB 2.0 hardware: 480 Mbps data rate, 8kHz USB bus microframe rate Data traffic: USB-to-WiFi adaptor, moving IPv4 frames through an IEEE 802.11ac connection. The IPv4 data traffic occupies 80Mbps of the wireless bandwidth. . Part 1 (2 pts): what is the peak programmed data transfer rate in bytes/second? Part 2 (2 pts): what is the peak DMA transfer rate in bytes/sec? Part 3 (2 pts): what is the data rate needed to keep the 802.11 connection busy in bytes/second? Part 4 (2 pts): how many bytes would need to be transferred per 8kHz USB microframe? Part 5 (2 pts): what is the DMA duty cycle? - what fraction of memory bandwidth is used? Question 6: DMA optimization: Compute and compare CPU memory transfers with DMA transfers to an IO device. Reminder: bps bits/second; not bytes/second) A microcontroller has the following characteristics: . ARM Cortex, single cycle 80 MHz clock, with one clock per instruction for most cases Programmed data transfer takes 4 cycles per 32-bit word DMA transfer capability, transferring 32-bits per memory clock USB 2.0 hardware: 480 Mbps data rate, 8kHz USB bus microframe rate Data traffic: USB-to-WiFi adaptor, moving IPv4 frames through an IEEE 802.11ac connection. The IPv4 data traffic occupies 80Mbps of the wireless bandwidth. . Part 1 (2 pts): what is the peak programmed data transfer rate in bytes/second? Part 2 (2 pts): what is the peak DMA transfer rate in bytes/sec? Part 3 (2 pts): what is the data rate needed to keep the 802.11 connection busy in bytes/second? Part 4 (2 pts): how many bytes would need to be transferred per 8kHz USB microframe? Part 5 (2 pts): what is the DMA duty cycle? - what fraction of memory bandwidth is used