please solve 16 , 17 only with steps

thanks in advanced

. . . O Consider an instruction set architecture with the following characteristics: Memory: byte-addressable, 16-bit addresses. Numbers: unsigned or signed (two's complement). Registers (16-bit): PC, SP and two general-purpose registers (RO, and R1). Instructions (variable-length): one-operand or two-operand. o One-operand instructions (16-bit): 4-bit opcode followed by one 12-bit operand. o Two-operand instructions (32-bit): 4-bit opcode followed by two 14-bit operands. Operand (12-bit): 2-bit addressing mode (AM) followed by 10-bit value/address (VA). o Operand (14-bit): 2-bit addressing mode (AM) followed by 12-bit value/address (VA). O Addressing-mode (2-bit): 00 immediate, 01 register, 10 indexed, 11 PC- relative (where register number is encoded by the least significant bit of VA whenever is needed). o Some of the supported operations: Opcode Operation Mnemonic (Decimal) Description Move MOV 8 First operand is destination. Second operand is source. First operand is the first source and the destination in Add ADD the same time. Second operand is the second source. 12 Note that the first operand cannot be a memory location. Increment INC 15 Operand specifies value to be incremented. 13) What is the length of the IR? A. 16 B. 24 C. 32 D. 48 14) How many different one-operand instructions that this processer could support? A. 16 B. 32 C. 64 D. 128 15) For one operand instructions, what is the range of numbers that an immediate operand can take? A. -1024 to 1023 B. -512 to 511 C.-2048 to 2047 D. None of them 16) The instruction INC RO, is stored in memory as ...... in hexadecimal A. 82 01 B. F2 00 C. F400 D. None of them 17) The instruction 84 00 40 07 in hexadecimal represents the instruction ... A. MOV R1, #7 B. ADD R1, #7 C. ADD #4, #7 D. None of them