Please solve 4.1 a , b and c.

1 Purpose To use FSMD methodology to design and implement an intermediate-sized digital circuit. Reading 2 Chapter 6 of FPGA Prototyping by VHDL Eramples 2d edition. Project specification The pupose of this project is to construct a circuit that counts number of 0's of a 10-bit input 3 word. For example, the output returns "0100 if the input is "0111001110". In addition to the clock and reset signals, the input signals of this circuit are start: one-bit command to initialize the counting a: 10-bit input data word The circuit outputs inchude the following ready: one-bit status indicating that the circuit is ready count: 4-bit result showing the number of O's in a. The design must be synchronous or 50% will be deducted. 4 Design Procedures 4.1 FSD design and simulation (a) Derive a pseudo algorithm. (b) Determine the registers needed. (c) Derive the detailed ASMD chart according to the algorithm. 1 Purpose To use FSMD methodology to design and implement an intermediate-sized digital circuit. Reading 2 Chapter 6 of FPGA Prototyping by VHDL Eramples 2d edition. Project specification The pupose of this project is to construct a circuit that counts number of 0's of a 10-bit input 3 word. For example, the output returns "0100 if the input is "0111001110". In addition to the clock and reset signals, the input signals of this circuit are start: one-bit command to initialize the counting a: 10-bit input data word The circuit outputs inchude the following ready: one-bit status indicating that the circuit is ready count: 4-bit result showing the number of O's in a. The design must be synchronous or 50% will be deducted. 4 Design Procedures 4.1 FSD design and simulation (a) Derive a pseudo algorithm. (b) Determine the registers needed. (c) Derive the detailed ASMD chart according to the algorithm