Please solve and explain in depth

Practice Problems for Processor

$3.$ The instruction code of a special$-$purpose processor$$s ISA uses $16$ bits to accommodate $3$ groups of

instructions: memory reference instructions, register reference instructions, and I$/$O instructions. The

instruction format is to be designed for processors with a main memory of $8$k $16-$bit words $($i$.$e$.$

addressable in word$).$ Memory reference instructions are all one$-$address instructions with two

addressing modes $($direct and indirect$)$ for the address, and there are a total of $2$ memory reference

instructions. The processors will have $16$ registers with $30$ register reference instructions. The register

reference instructions have both one$-$address and two$-$addresses instructions with two addressing

modes $($register direct and register indirect$)$ for each register address in a register reference instruction.

There need to be $4$ input instructions and $4$ output instructions.

The design of the instruction format for this computer has been partially done as follows:

Denote $16-$bit the instruction code by $($R$15,$ R$14,...,$ R$0).$

a$.$ A memory reference instruction has$13$ address bits $($R$12,$ R$11,...,$ R$0).$ R$13$ is the bit for indicating

the address mode of a memory reference instruction with R$13=0$ indicting direct mode and R$13=1$

indicating indirect mode.

b$.$ When R$15=0,$ the instruction is a memory reference instruction. When R$15=1,$ the instruction is

either a register reference instruction or an I$/$O instruction.

c$.$ For a register reference instruction, we set aside the $8$ bits $($R$7,$R$6,...,$ R$0)$ for the address bits for

both one$-$address and two$-$addresses instructions with a one$-$address instruction being specified by

$($R$7,$R$6,$R$5,$R$4)=($R$3,$R$2,$R$1,$R$0).$ Bits R$8,$ R$9$ are used as the addressing$-$mode bits for register reference

instructions with R$8=0$ indicating register direct mode for bits $($R$3,$R$2,$R$1,$R$0)$ and R$8=1$ indicating

indirect register mode for bits $($R$3,$R$2,$R$1,$R$0)$; R$9=0$ indicating register direct mode

$\backslash$ for bits

$($R$7,$R$6,$R$5,$R$4)$ and R$9=1$ indicating indirect register mode for bits $($R$7,$R$6,$R$5,$R$4).$

d$.$ For an I$/$O instruction, bit R$8$ is the I$-$or$-$O bit with R$8=0$ indicating an input instruction and R$8=1$

indicating an output instruction. Bits $($R$7,$ R$6)$ specify the I$/$O operation, and the bits $($R$5,$ R$4,$ R$3,$ R$2,$

R$1,$R$0)$ specify the port$/$device involved in the input or output operation.

With the partial design of instruction format, answer the following questions.

$($ i $)$ Give a design of the instruction bits $($R$14,$ R$13,$ R$12,$R$11,$R$10)$ so that both the $30$ register

instructions can be accommodated and an indication of a register instruction or I$/$O instruction can

also be provided.

$($i i$)$ What is the maximal number of input ports$/$devices this ISA allows?

$($iii$)$ To carry out a direct addressing memory reference instruction, how many references to memory is

needed? $($Suppose no virtual memory and the instruction is already in CPU and decoded$)$ How

many memory references is needed for an indirect address instruction?

$($iv$)$ If the memory address $100000010010$ has content $0000100000000000,$ what is effective address

of the instruction $(0010100000010010)?$