please solve as soon as possible ... thank you

Given the following ASM Chart: S T1 A Input1 B + Input2 N = Input3 F+0 T2 A+ A+ B T3 z 14 0 SHR B by 1 bit SHR N by 1 bit T5 :XOR SHR: Shift Right A: 16 bits Storage Register B,N: 16 bits Shift Registers No: The Least Significant Bit of N Z: The zero signal is set to (1) when the value of shift register N is zero 1) Design the data processor (You have to show the data source and the control signals for each component. (10 Points) 2) Design the controller using one flip-flop per state (You have to show the clock and the reset signals) (5 Points)