please solve asap (embedded systems course)

Q3 (4 marks): An ARM assembly code consists of following instructions: MOV RS, #16 MOV R4,0x200 L1: LDR R1, (R4) ADD RS, RS, #2 CMP RS, #20 BNE L1 ADD R2, R3, #10 CMP R2, #30 Please draw the diagram to illustrate the execution and the corresponding data/control stalls of the program on an ARMv7 3-stage pipeline. How many clock cycles would it take to complete the program? Assume that LDR instruction requires three clock cycles to execute. The rest of the instructions takes one clock cycle each to execute. Assume that fetching and decoding can be performed in one clock cycle each. You can use F for Instruction Eetch, D for Instruction Decode and X for Execution units in your diagram