please solve this digital project with verilog hdl using data flow

please do not use truth table and do not copy from others

thanks in afvance

In this project, you need to implement a BCD adder-subtractor circuit shown in Figure 1. You need to build the system components separately using Verilog HDL. Then, you have to integrate the different system components to build the whole system. Each of the system components, as well as, the whole system should be verified using simulation. BBBB Mode - O FOR Add Mode - / for Swar 9's Complementer (See Problem 4.18) Select Select Chandrapl.2 x / MUX BCD Aur (SP. 4140 Figure 1 BCD adder-subtractor circuit A. Design a combinational circuit that generates the 9's complement of a BCD digit. Develop and simulate a data flow model (don't use the behavioral model for this component) of a circuit that generates the 9's complement B. Design a combinational circuit that describes the quadruple 2x1 multiplexer using a behavioral model. Develop and simulate a behavioral model (don't use the data flow model for this component). C. Design a combinational circuit for BCD adder. See Figure 4.14 of the textbook for the whole design of the BCD adder. Develop and simulate a data flow model (don't use the behavioral model for this component) for the BCD adder. D. Integrate the whole components of the system by developing and simulating a structural model of Figure 1. In your design, make sure that (1) the BCD adder should be described as a data flow model in a separate module, (2) the 9's complementor should be described as data flow model in a separate module, and (3) the quadruple 2X1 multiplexer be described as a behavioral model in a separate module. Finally, all the system components are to be instantiated in a top-level module using a structural model