please solve this question

Multiple Choice: -Put answers to the left of the question, Choose the best answer for each(3 points each) 1 If both S and R inputs of a clocked SR Latch are ZERO, what will happen when the clock goes ONE? A. No change will occur in the output. B A C The output will toggle D. The output will reset An invalid state will exist. 2 AS-R latch has a 1 on the S input and a 0 on the R input. What state will the latch be in? C Q-71 3. If both inputs of an s'-r' Latch are ZERO, what will happen when the clock goes ONE? A. B. An invalid state will exist No change will occur in the output C The output will toggle D. The output will reset 4. A s.r' latch has a 0 on the s input and a l on the r, snpu. what state will te latch be in? C. Q-7,Q'? 5. A s-r' latch has a 1 on the s. input and a 0 on the r input what state is the latch in? 6 Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? A. The logic level at the D input is transferred to Q when Clock changes from ONE to ZERO B. Tbe Q output is ALWAYS identical to the CLK imput if the D input is ONE C The Q output is ALWAYS identical to the D input when CLK changes from ZERO to ONE D The Q output is ALWAYS identical to the D input 7. A controlled (EN) S-R latch and its associated waveforms are shown below. Is anything wrong with it? L-??-LI- A. The q' output is always ZERO; the circuit is defective B. The Q output should be the complement of the Q output the S and R terminals are reversed EN The Q should be followingthe R 1npu; the R imput is defective C. D. There is nothing wrong with the circuit ?? ? ? EN