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The task is to design a structural comparator for signed and unsigned number and then

to write a complete code for verification. You should search for information about the needed

logic$/$circuits to implement a comparator for signed and unsigned numbers.

The Task:

Your task is to structurally create a comparator for signed numbers $(2\text{'}$s complement

representation$)$ and unsigned numbers. The circuit will have the following main inputs and

outputs

$1-$ First number A: $6$ bits

$2-$ Second number B: $6$ bits

$3-$ Selection S: $1$ bit to select how to consider the numbers $($signed or unsigned$)$ and

thus how comparator will work

$4-$ First output "Equal" $\_()$ will produce $1$ if A$=$B$.$

$5-$ Second output "Greater": will produce $1$ if A $>$ B$.$

$6-$ Third output "Smaller": will produce $1$ if A $$ B$.$

The Comparator is to be built structurally from a library of gates, which contains the

following devices:

All combinational parts of your design should be built structurally from these basic gates

and the defined delays $($consider that the delay will not change even if the gate has more than

$2$ inputs$).$

After that registers should be added to the inputs$/$outputs of the circuit to make the circuit

synchronous $($thus$,$ we need to add more inputs such as clk$).$

You should determine the maximum latency of the comparator. And therefore, what is

the maximum frequency of the clock that can be applied to the registers. You should verify

that your system is working for all possible values of the inputs. Also, you should introduce

an error in your design and to do a verification that will discover the error and write it to the

console screen.

Format of the report:

This project should be written as formal report. The report should include sections on

the following:

Brief introduction

Brief theoretical overview

Design philosophy

Simulation Results

Conclusion and Future works

The report shouldn't exceed $10$ pages $($excluding the code$)$ with

$1\mathrm{.}5$ line spacing.

Times new roman.

Font $=12$ point

The code and report should be sent on Bitai before deadline.

Key Points:

Any type of plagiarism will be penalized by $0$ mark, and the cheaters will be treated

according to the university laws.

The design description should include a block diagram of the design, and give a

justification of the decisions made.

Technical achievement in design is linked to the degree of functionality that was

attempted.

Technical achievement in implementation is based on the quality of your Verilog

code. This includes issues such as legibility of code, use of meaningful variable

names, good comments, clear structure, and modifiability of the design.

Technical achievement in evaluation is based on the quality of your simulation

results.