Please write the entity-architectures in VHDL

(Reset)R (nq) (Set) S SR Latch 1) Assume each gate is 5 ns delay for the above circuit. (a) Write entity-architecture for a inertial model (b) Given the following waveform, draw, R, S, Q, NQ (inertial) (c) Repeat (b) but now assume ea (d) Write entity-architecture for a transport model (e) Given the waveform in (b) draw, R, S, Q, NQ (transport) (Reset)R (nq) (Set) S SR Latch 1) Assume each gate is 5 ns delay for the above circuit. (a) Write entity-architecture for a inertial model (b) Given the following waveform, draw, R, S, Q, NQ (inertial) (c) Repeat (b) but now assume ea (d) Write entity-architecture for a transport model (e) Given the waveform in (b) draw, R, S, Q, NQ (transport)