Pre$-$lab:

$1.$ Develop an algorithm for performing $8-$bit floating$-$point addition. $(10$ points$)$

$2.$ Draw an FSMD depicting your algorithm $($see Figure $10\mathrm{.}1$ for an example$).(10$ points$)$

$3.$ Draw a datapath for implementing your FSMD$.(10$ points$)$

$4.$ Draw the state diagram, along with the control$/$status signals, for your controller. $(10$ points$)$

$5.$ Develop Verilog code for your FSM$+$Datapath design. $(20$ points, controller, datapath, both

combine$)$

$6.$ Simulate and verify your design with a minimum of $4$ different test cases. $(10$ points total$)$