Prelab (Every group member should do the prelab) 1. Write the truth tables for the following D latch and J-K flip-flops shown below Output J-K flip-flop clk D Latch Q Ci IK Inputs Inputs 2. Using a maximum of two JK flip-flops and no other registers, design a 2-bit counter with an active high reset signal. You can use any method such as circuit diagrams, logic tables, K-maps, etc. for this part as you see fit. Just be sure you are able to translate your design to VHDL code for lab. Also include an active high signal to reset the counter. The counter should run from 0 to 3 and then back to 0