Prepare a flow chart that will count the number of $1\text{'}$s in register, Rc$,$ and then store the counts in $[7\mathrm{.}5]$ register $Rd.$

Determine the outputs of the Rc $($in binary$)$ and Rd $($in decimal$)$ registers as well as of the carry flag after each clock cycle or timing state. Determine the number of states that are required to complete the operation.

$\backslash$table$[[$Timing States,Rc$,\frac{C}{1},\backslash$table$[[Rd$